The present invention relates to a sense amplifier circuit for sensing read data in a memory device.
High-speed sense amplifier circuits which operate stably in memory devices such as an SRAM, a DRAM, and a ROM have been in growing demand. As system LSIs have increased in the degree of integration, a higher density has been required particularly of the SRAM which is requested to perform a high-speed and stable read operation even if a cell current is reduced by reductions in the area and voltage of a memory cell.
An example of a full-latch sense amplifier circuit is disclosed in Japanese Unexamined Patent Publication No. HEI 11-283377. The full-latch sense amplifier comprises: a CMOS latch for amplifying the potential difference between a pair of output nodes in response to potential changes on a pair of bitlines which represent data stored in a memory cell; and a bitline disconnecting circuit for cutting off a feedback of the potentials from the pair of output nodes to the pair of bitlines. The bitline disconnecting circuit is composed of a pair of PMOS transistors interposed between the pair of bitlines and the CMOS latch. The pair of PMOS transistors function to reduce a load on the CMOS latch by disconnecting the CMOS latch from the pair of bitlines when the CMOS latch is activated. In short, the pair of PMOS transistors allow the CMOS latch to perform a high-speed amplifying operation by disconnecting the CMOS latch from the pair of bitlines at the time at which a small potential difference responsive to potential changes on the pair of bitlines occurs between the pair of output nodes and activating the CMOS latch.
While the pair of PMOS transistors composing the bitline disconnecting circuit function to increase the amplifying speed after the activation of the CMOS latch, they cause a delay in data transfer due to the resistive components of their own. To reduce the resistive components, the PMOS transistors should be increased in size. However, the increased size has a side effect of increasing coupling noise upon disconnection or the like. Therefore, it has conventionally been inevitable to tolerate a given delay time in data transfer.
It is therefore an object of the present invention to improve high-speed property and stability of a sense amplifier circuit, while allowing a bitline disconnecting circuit to have effects that have been obtained conventionally.
To attain the object, a sense amplifier circuit according to an embodiment of the present invention is configured such that the gate or source electrodes of MOS transistors composing a latch is coupled directly to bitlines without the interposition of a bitline disconnecting circuit therebetween.